FUNCTIONAL BLOCK DIAGRAM

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA BUS

DMA BUS

SERIAL PORTS

SPORT 1

SPORT 0

MEMORY

PROGRAM

MEMORY

DATA

MEMORY

PROGRAMMABLE

I/O

FLAGS

BYTE DMA

CONTROLLER

TIMER

ADSP-2100 BASE

ARCHITECTURE

SHIFTER

MAC

ALU

ARITHMETIC UNITS

POWER-DOWN

CONTROL

PROGRAM

SEQUENCER

DAG 2

DAG 1

DATA ADDRESS

GENERATORS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

INTERNAL

DMA

PORT

DSP Microcomputer

ADSP-2181

FEATURES
PERFORMANCE
25 ns Instruction Cycle Time from 20 MHz Crystal

@ 5.0 Volts

40 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 100 Cycle Recovery from
Power-Down Condition

Low Power Dissipation in Idle Mode

INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction

Set Extensions

80K Bytes of On-Chip RAM, Configured as

16K Words On-Chip Program Memory RAM
16K Words On-Chip Data Memory RAM

Dual Purpose Program Memory for Both Instruction

and Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units

Two Independent Data Address Generators
Powerful Program Sequencer Provides

Zero Overhead Looping
Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler
128-Lead TQFP/128-Lead PQFP

SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to

On-Chip Memory

4 MByte Memory Interface for Storage of Data Tables

and Program Overlays

8-Bit DMA to Byte Memory for Transparent

Program and Data Memory Transfers

I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals

Programmable Memory Strobe and Separate I/O Memory

Space Permits "Glueless" System Design

Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port

Six External Interrupts
13 Programmable Flag Pins Provide Flexible System

Signaling

ICE-PortTM Emulator Interface Supports Debugging

in Final Systems

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

ICE-Port is a trademark of Analog Devices, Inc.

GENERAL DESCRIPTION

The ADSP-2181 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.

The ADSP-2181 combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and data
memory.

The ADSP-2181 integrates 80K bytes of on-chip memory con-
figured as 16K words (24-bit) of program RAM, and 16K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip-
ment. The ADSP-2181 is available in 128-lead TQFP and 128-
lead PQFP packages.

In addition, the ADSP-2181 supports new instructions, which
include bit manipulations--bit set, bit clear, bit toggle, bit test--
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking for increased flexibility.

Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2181 operates with a 25 ns instruction cycle
time. Every instruction can execute in a single processor cycle.

The ADSP-2181's flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2181 can:

· Generate the next program address

· Fetch the next instruction

· Perform one or two data moves

· Update one or two data address pointers

· Perform a computational operation

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1998

REV. D

ADSP-2181

This takes place while the processor continues to:

· Receive and transmit data through the two serial ports
· Receive and/or transmit data through the internal DMA port
· Receive and/or transmit data through the byte DMA port
· Decrement timer

Development System

The ADSP-2100 Family Development Software, a complete
set of tools for software and hardware system development,
supports the ADSP-2181. The System Builder provides a high
level method for defining the architecture of systems under
development. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into
an executable file. The Simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
PROM Splitter generates PROM programmer compatible files.
The C Compiler, based on the Free Software Foundation's
GNU C Compiler, generates ADSP-2181 assembly source
code. The source code debugger allows programs to be cor-
rected in the C environment. The Runtime Library includes over
100 ANSI-standard mathematical and DSP-specific functions.

The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-2181 evaluation board with PC monitor software plus
Assembler, Linker, Simulator, and PROM Splitter software.
The ADSP-218x EZ-KIT Lite is a low-cost, easy to use hard-
ware platform on which you can quickly get started with your
DSP software design. The EZ-KIT Lite includes the following
features:

· 33 MHz ADSP-2181
· Full 16-bit Stereo Audio I/O with AD1847 SoundPort

Codec

· RS-232 Interface to PC with Windows 3.1 Control Software
· Stand-Alone Operation with Socketed EPROM
· EZ-ICE

Connector for Emulator Control

· DSP Demo Programs

The ADSP-218x EZ-ICE

Emulator aids in the hardware debug-

ging of ADSP-218x systems. The emulator consists of hard-
ware, host computer resident software and the target board
connector. The ADSP-218x integrates on-chip emulation sup-
port with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection requiring fewer mechanical
clearance considerations than other ADSP-2100 Family EZ-ICEs.
The ADSP-218x device need not be removed from the target
system when using the EZ-ICE, nor are any adapters needed. Due
to the small footprint of the EZ-ICE

connector, emulation can be

supported in final board designs.

The EZ-ICE

performs a full range of functions, including:

· In-target operation
· Up to 20 breakpoints
· Single-step or full-speed operation
· Registers and memory values can be examined and altered
· PC upload and download functions
· Instruction-level emulation of program booting and execution
· Complete assembly and disassembly of instructions
· C source-level debugging

See the Designing An EZ-ICE-Compatible Target System sec-
tion of this data sheet for exact specifications of the EZ-ICE target
board connector.

Additional Information

This data sheet provides a general overview of ADSP-2181
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User's Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development
Tools Data Sheet.

ARCHITECTURE OVERVIEW

The ADSP-2181 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The ADSP-2181 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.

Figure 1 is an overall block diagram of the ADSP-2181. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations. The shifter can be used to efficiently implement
numeric format control including multiword and block floating-
point representations.

The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computa-
tional units. The sequencer supports conditional jumps, subroutine
calls and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2181 executes looped code with zero over-
head; no explicit jump instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.

Efficient data transfer is achieved with the use of five internal
buses:

· Program Memory Address (PMA) Bus
· Program Memory Data (PMD) Bus
· Data Memory Address (DMA) Bus
· Data Memory Data (DMD) Bus
· Result (R) Bus

The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.

Program memory can store both instructions and data, permit-
ting the ADSP-2181 to fetch two operands in a single cycle,
one from program memory and one from data memory. The

EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.

ADSP-2181

REV. D

ADSP-2181 can fetch an operand from program memory and
the next instruction in the same cycle.

In addition to the address and data bus for external memory
connection, the ADSP-2181 has a 16-bit Internal DMA port
(IDMA port) for connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.

An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with program-
mable wait state generation. External devices can gain control of
external buses with bus request/grant signals (

BR, BGH and BG).

One execution mode (Go Mode) allows the ADSP-2181 to con-
tinue running from on-chip memory. Normal execution mode
requires the processor to halt while buses are granted.

The ADSP-2181 can respond to 13 possible interrupts, eleven
of which are accessible at any given time. There can be up to six
external interrupts (one edge-sensitive, two level-sensitive and
three configurable) and seven internal interrupts generated by
the timer, the serial ports (SPORTs), the Byte DMA port and
the power-down circuitry. There is also a master

RESET signal.

The two serial ports provide a complete synchronous serial inter-
face with optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.

The ADSP-2181 provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.

A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycles, where n is a scaling value stored in an 8-bit regis-
ter (TSCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-2181 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2181 SPORTs.
Refer to the ADSP-2100 Family User's Manual, Third Edition for
further details.

· SPORTs are bidirectional and have a separate, double-

buffered transmit and receive section.

· SPORTs can use an external serial clock or generate their

own serial clock internally.

· SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.

OUTPUT REGS

ALU

OUTPUT REGS

MAC

TIMER

INPUT REGS

ADSP-2181 INTEGRATION

DATA

ADDRESS

GENERATOR

DATA

ADDRESS

GENERATOR

21xx CORE

PMA BUS

DMA BUS

PMD BUS

INSTRUCTION

REGISTER

PROGRAM

SEQUENCER

BUS

EXCHANGE

DMD BUS

PROGRAM

SRAM

16K

DATA

SRAM

16K

BYTE

DMA

CONTROLLER

MUX

DMD

BUS

PMA BUS

DMA BUS

PMD BUS

INPUT REGS

SHIFTER

OUTPUT REGS

INPUT REGS

MAC

OUTPUT REGS

INPUT REGS

ALU

OUTPUT REGS

R BUS

TRANSMIT REG

RECEIVE REG

SERIAL
PORT 0

TRANSMIT REG

RECEIVE REG

SERIAL
PORT 0

COMPANDING

CIRCUITRY

INTERNAL

DMA

PORT

INTERRUPTS

POWER-

DOWN

CONTROL

LOGIC

MUX

PROGRAMMABLE

I/O

FLAGS

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

Figure 1. ADSP-2181 Block Diagram

REV. D

ADSP-2181

· SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and

-law companding according

to CCITT recommendation G.711.

· SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

· SPORTs can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.

· SPORT0 has a multichannel interface to selectively receive

and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.

· SPORT1 can be configured to have two external interrupts

(

IRQ0 and IRQ1) and the Flag In and Flag Out signals. The

internally generated serial clock may still be used in this
configuration.

Pin Descriptions

The ADSP-2181 is available in 128-lead TQFP and 128-lead
PQFP packages.

PIN FUNCTION DESCRIPTIONS

Pin

Input/

Name(s)

Pins

Output Function

Address

Address Output Pins for Program,

Data, Byte, and I/O Spaces

Data

I/O

Data I/O Pins for Program and
Data Memory Spaces (8 MSBs
Are Also Used as Byte Space
Addresses)

RESET

Processor Reset Input

IRQ2

Edge- or Level-Sensitive
Interrupt Request

IRQL0,

IRQL1

Level-Sensitive Interrupt
Requests

IRQE

Edge-Sensitive Interrupt
Request

Bus Request Input

Bus Grant Output

BGH

Bus Grant Hung Output

PMS

Program Memory Select Output

DMS

Data Memory Select Output

BMS

Byte Memory Select Output

IOMS

I/O Space Memory Select Output

CMS

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

MMAP

Memory Map Select Input

BMODE

Boot Option Control Input

CLKIN,
XTAL

Clock or Quartz Crystal Input

Pin

Input/

Name(s)

Pins

Output Function

CLKOUT

Processor Clock Output

SPORT0

I/O

Serial Port I/O Pins

SPORT1

I/O

Serial Port 1 or Two External
IRQs, Flag In and Flag Out

IRD, IWR 2

IDMA Port Read/Write Inputs

IDMA Port Select

IAL

IDMA Port Address Latch
Enable

IAD

I/O

IDMA Port Address/Data Bus

IACK

IDMA Port Access Ready
Acknowledge

PWD

Power-Down Control

PWDACK 1

Power-Down Control

FL0, FL1,
FL2

Output Flags

PF7:0

I/O

Programmable I/O Pins

(Emulator Only*)

EBR

(Emulator Only*)

EBG

(Emulator Only*)

ERESET

(Emulator Only*)

EMS

(Emulator Only*)

EINT

(Emulator Only*)

ECLK

(Emulator Only*)

ELIN

(Emulator Only*)

ELOUT

(Emulator Only*)

GND

Ground Pins

VDD

Power Supply Pins

*These ADSP-2181 pins must be connected only to the EZ-ICE

connector in

the target system. These pins have no function except during emulation, and
do not require pull-up or pull-down resistors.

Interrupts

The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2181 provides four dedicated external interrupt
input pins,

IRQ2, IRQL0, IRQL1 and IRQE. In addition,

SPORT1 may be reconfigured for

IRQ0, IRQ1, FLAG_IN and

FLAG_OUT, for a total of six external interrupts. The ADSP-
2181 also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power down and reset). The
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be
either level- or edge-sensitive.

IRQL0 and IRQL1 are level-

sensitive and

IRQE is edge sensitive. The priorities and vector

addresses of all interrupts are shown in Table I.

ADSP-2181

REV. D

Table I. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

Source of Interrupt

Address (Hex)

Reset (or Power-Up with PUCR = 1) 0000

(Highest Priority)

Power-Down (Nonmaskable)

002C

IRQ2

0004

IRQL1

0008

IRQL0

000C

SPORT0 Transmit

0010

SPORT0 Receive

0014

IRQE

0018

BDMA Interrupt

001C

SPORT1 Transmit or

IRQ1

0020

SPORT1 Receive or

IRQ0

0024

Timer

0028

(Lowest Priority)

Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.

The ADSP-2181 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.

The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the

IRQ0, IRQ1 and IRQ2 external interrupts to

be either edge- or level-sensitive. The

IRQE pin is an external

edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.

The IFC register is a write-only register used to force and clear
interrupts.

On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. The stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.

The following instructions allow global enable or disable servic-
ing of the interrupts (including power down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.

ENA INTS;
DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The ADSP-2181 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:

· Power-Down

· Idle

· Slow Idle

The CLKOUT pin may also be disabled to reduce external
power dissipation.

Power-Down

The ADSP-2181 processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-
down features. For detailed information about the power-
down feature, refer to the ADSP-2100 Family User's Manual,
Third Edition, "System Interface" chapter.

· Quick recovery from power-down. The processor begins

executing instructions in as few as 100 CLKIN cycles.

· Support for an externally generated TTL or CMOS

processor clock. The external clock can continue running
during power-down without affecting the lowest power
rating and 100 CLKIN cycle recovery.

· Support for crystal operation includes disabling the oscil-

lator to save power (the processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabi-
lize), and letting the oscillator run to allow 100 CLKIN
cycle start up.

· Power-down is initiated by either the power-down pin

(

PWD) or the software power-down force bit.

· Interrupt support allows an unlimited number of instruc-

tions to be executed before optionally powering down.
The power-down interrupt also can be used as a non-
maskable, edge-sensitive interrupt.

· Context clear/save control allows the processor to con-

tinue where it left off or start with a clean context when
leaving the power-down state.

· The

RESET pin also can be used to terminate power-

down.

· Power-down acknowledge pin indicates when the proces-

sor has entered power-down.

Idle

When the ADSP-2181 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE instruction.

Slow Idle

The IDLE instruction is enhanced on the ADSP-2181 to let
the processor's internal clock signal be slowed, further
reducing power consumption. The reduced clock fre-
quency, a programmable fraction of the normal clock rate,
is specified by a selectable divisor given in the IDLE in-
struction. The format of the instruction is

IDLE (n);

where n = 16, 32, 64 or 128. This instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor's other internal
clock signals, such as SCLK, CLKOUT and timer clock,
are reduced by the same ratio. The default form of the
instruction, when no clock divisor is given, is the standard
IDLE instruction.

REV. D

ADSP-2181

When the IDLE (n) instruction is used, it effectively slows down
the processor's internal clock and thus its response time to in-
coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2181 will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor's reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).

SYSTEM INTERFACE

Figure 2 shows a typical basic system configuration with the
ADSP-2181, two serial devices, a byte-wide EPROM, and op-
tional external program and data overlay memories. Program-
mable wait state generation allows the processor to connect
easily to slow peripheral devices. The ADSP-2181 also provides
four external interrupts and two serial ports or six external inter-
rupts and one serial port.

1/2x CLOCK

CRYSTAL

SERIAL
DEVICE

A0-A21

DATA

BYTE

MEMORY

I/O SPACE

(PERIPHERALS)

DATA

ADDR

DATA

ADDR

2048 LOCATIONS

OVERLAY

MEMORY

TWO 8K

PM SEGMENTS

TWO 8K

DM SEGMENTS

23-0

13-0

23-8

10-0

15-8

23-16

13-0

SPORT1

SCLK0
RFS0
TFS0
DT0
DR0

SPORT0

IAD15-0

IDMA PORT

FL0-2
PF0-7

CLKIN

XTAL

ADDR13-0

DATA23-0

BMS

IOMS

ADSP-2181

IRQ2
IRQE
IRQL0
IRQL1

PMS

DMS
CMS

BGH

PWD

PWDACK

IRD

IWR

IAL

IACK

SCLK1
RFS1 OR

IRQ0

TFS1 OR

IRQ1

DT1 OR FO
DR1 OR FI

SYSTEM

INTERFACE

CONTROLLER

Figure 2. ADSP-2181 Basic System Configuration

Clock Signals

The ADSP-2181 can be clocked by either a crystal or a TTL-
compatible clock signal.

The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User's Manual, Third Edition, for detailed
information on this power-down feature.

If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor's CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.

The ADSP-2181 uses an input clock with a frequency equal to
half the instruction rate; a 20.00 MHz input clock yields a 25 ns
processor cycle (which is equivalent to 40 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.

Because the ADSP-2181 includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.

A clock output (CLKOUT) signal is generated by the processor
at the processor's cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.

CLKIN

CLKOUT

XTAL

DSP

Figure 3. External Crystal Connections

Reset

The

RESET signal initiates a master reset of the ADSP-2181.

The

RESET signal must be asserted during the power-up se-

quence to assure proper initialization.

RESET during initial

power-up must be held long enough to allow the internal clock
to stabilize. If

RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V

is ap-

plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the

RESET signal should be held low. On

any subsequent resets, the

RESET signal must meet the mini-

mum pulse width specification, t

RSP

The

RESET input contains some hysteresis; however, if you use

an RC circuit to generate your

RESET signal, the use of an

external Schmidt trigger is recommended.

The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When

RESET is released, if there is no pending bus

request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000 once
boot loading completes.

ADSP-2181

REV. D

Table II.

PMOVLAY Memory

A13

A12:0

Internal

Not Applicable

External

13 LSBs of Address

Overlay 1

Between 0x2000
and 0x3FFF

External

13 LSBs of Address

Overlay 2

Between 0x2000
and 0x3FFF

This organization provides for two external 8K overlay segments
using only the normal 14 address bits. This allows for simple
program overlays using one of the two external segments in
place of the on-chip memory. Care must be taken in using this
overlay space in that the processor core (i.e., the sequencer)
does not take into account the PMOVLAY register value. For
example, if a loop operation was occurring on one of the exter-
nal overlays and the program changes to another external over-
lay or internal memory, an incorrect loop operation could occur.
In addition, care must be taken in interrupt service routines as
the overlay registers are not automatically saved and restored on
the processor mode stack.

For ADSP-2100 Family compatibility, MMAP = 1 is allowed.
In this mode, booting is disabled and overlay memory is dis-
abled (PMOVLAY must be 0). Figure 5 shows the memory map
in this configuration.

INTERNAL 8K

(PMOVLAY = 0,

MMAP = 1)

0x3FFF

0x2000

0x1FFF

8K EXTERNAL

0x0000

PROGRAM MEMORY

ADDRESS

Figure 5. Program Memory (MMAP = 1)

Data Memory

The ADSP-2181 has 16,352 16-bit words of internal data
memory. In addition, the ADSP-2181 allows the use of 8K
external memory overlays. Figure 6 shows the organization of
the data memory.

8K INTERNAL

(DMOVLAY = 0)

EXTERNAL 8K

(DMOVLAY = 1, 2)

INTERNAL

8160 WORDS

DATA MEMORY

ADDRESS

32 MEMORY

MAPPED REGISTERS

0x3FFF

0x3FEO

0x3FDF

0x2000

0x1FFF

0x0000

Figure 6. Data Memory

Memory Architecture

The ADSP-2181 provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory and I/O.

Program Memory is a 24-bit-wide space for storing both
instruction opcodes and data. The ADSP-2181 has 16K words
of Program Memory RAM on chip and the capability of access-
ing up to two 8K external memory overlay spaces using the
external data bus. Both an instruction opcode and a data value
can be read from on-chip program memory in a single cycle.

Data Memory is a 16-bit-wide space used for the storage of
data variables and for memory-mapped control registers. The
ADSP-2181 has 16K words on Data Memory RAM on chip,
consisting of 16,352 user-accessible locations and 32 memory-
mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus.

Byte Memory provides access to an 8-bit wide memory space
through the Byte DMA (BDMA) port. The Byte Memory inter-
face provides access to 4 MBytes of memory by utilizing eight
data lines as additional address lines. This gives the BDMA Port
an effective 22-bit address range. On power-up, the DSP can
automatically load bootstrap code from byte memory.

I/O Space allows access to 2048 locations of 16-bit-wide data.
It is intended to be used to communicate with parallel periph-
eral devices such as data converters and external registers or
latches.

Program Memory

The ADSP-2181 contains a 16K

24 on-chip program RAM.

The on-chip program memory is designed to allow up to two
accesses each cycle so that all operations can complete in a
single cycle. In addition, the ADSP-2181 allows the use of 8K
external memory overlays.

The program memory space organization is controlled by the
MMAP pin and the PMOVLAY register. Normally, the ADSP-
2181 is configured with MMAP = 0 and program memory orga-
nized as shown in Figure 4.

8K INTERNAL

(PMOVLAY = 0,

MMAP = 0)

EXTERNAL 8K

(PMOVLAY = 1 or 2,

MMAP = 0)

0x3FFF

0x2000

0x1FFF

8K INTERNAL

0x0000

PROGRAM MEMORY

ADDRESS

Figure 4. Program Memory (MMAP = 0)

There are 16K words of memory accessible internally when the
PMOVLAY register is set to 0. When PMOVLAY is set to
something other than 0, external accesses occur at addresses
0x2000 through 0x3FFF. The external address is generated as
shown in Table II.

REV. D

ADSP-2181

The

CMS pin functions like the other memory select signals,

with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the

CMS signal at the same time as the

selected memory select signal. All enable bits, except the

BMS

bit, default to 1 at reset.

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 pages, each of which is 16K

The byte memory space on the ADSP-2181 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg

8 (32 megabit) ROM or RAM to be

used without glue logic. All byte memory accesses are timed by
the BMWAIT register.

Byte Memory DMA (BDMA)

The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally, and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.

The BDMA circuit supports four different data formats which
are selected by the BTYPE register field. The appropriate num-
ber of 8-bit accesses are done from the byte memory space to
build the word size selected. Table V shows the data formats
supported by the BDMA circuit.

Table V.

Internal

BTYPE

Memory Space

Word Size

Alignment

Program Memory

Full Word

Data Memory

Full Word

Data Memory

MSBs

Data Memory

LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always be
on-chip program or data memory, regardless of the values of
MMAP, PMOVLAY or DMOVLAY.

There are 16,352 words of memory accessible internally when
the DMOVLAY register is set to 0. When DMOVLAY is set to
something other than 0, external accesses occur at addresses
0x0000 through 0x1FFF. The external address is generated as
shown in Table III.

Table III.

DMOVLAY

Memory

A13

A12:0

Internal

Not Applicable

External

13 LSBs of Address

Overlay 1

Between 0x0000
and 0x1FFF

External

13 LSBs of Address

Overlay 2

Between 0x0000
and 0x1FFF

This organization allows for two external 8K overlays using only
the normal 14 address bits.

All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
register.

I/O Space

The ADSP-2181 supports an additional external memory space
called I/O space. This space is designed to support simple con-
nections to peripherals or to bus interface ASIC data registers.
I/O space supports 2048 locations. The lower eleven bits of the
external address bus are used; the upper three bits are unde-
fined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0-3, which specify up to seven wait states to
be automatically generated for each of four regions. The wait
states act on address ranges as shown in Table IV.

Table IV.

Address Range

Wait State Register

0x0000x1FF

IOWAIT0

0x2000x3FF

IOWAIT1

0x4000x5FF

IOWAIT2

0x6000x7FF

IOWAIT3

Composite Memory Select (

CMS)

The ADSP-2181 has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. The

CMS signal is generated

to have the same timing as each of the individual memory select
signals (

PMS, DMS, BMS, IOMS) but can combine their

functionality.

When set, each bit in the CMSSEL register, causes the

CMS

signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the

CMS pin to drive the chip select

of the memory; use either

DMS or PMS as the additional

address bit.

ADSP-2181

REV. D

Table VI. Boot Summary Table

MMAP

BMODE

Booting Method

BDMA feature is used in default mode
to load the first 32 program memory
words from the byte memory space.
Program execution is held off until all
32 words have been loaded.

IDMA feature is used to load any inter-
nal memory as desired. Program execu-
tion is held off until internal program
memory location 0 is written to.

Bootstrap features disabled. Program
execution immediately starts from
location 0.

BDMA Booting

When the BMODE and MMAP pins specify BDMA booting
(MMAP = 0, BMODE = 0), the ADSP-2181 initiates a BDMA
boot sequence when reset is released. The BDMA interface is
set up during reset to the following defaults when BDMA boot-
ing is specified: the BDIR, BMPAGE, BIAD and BEAD regis-
ters are set to 0, the BTYPE register is set to 0 to specify
program memory 24 bit words, and the BWCOUNT register is
set to 32. This causes 32 words of on-chip program memory to
be loaded from byte memory. These 32 words are used to set up
the BDMA to load in the remaining program code. The BCR
bit is also set to 1, which causes program execution to be held
off until all 32 words are loaded into on-chip program memory.
Execution then begins at address 0.

The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface.

IDMA Booting
The ADSP-2181 can also boot programs through its Internal
DMA port. If BMODE = 1 and MMAP = 0, the ADSP-2181
boots from the IDMA port. IDMA feature can load as much on-
chip memory as desired. Program execution is held off until on-
chip program memory location 0 is written to.

The ADSP-2100 Family Development Software (Revision 5.02
and later) can generate IDMA compatible boot code.

Bus Request and Bus Grant

The ADSP-2181 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (

BR) signal. If the

ADSP-2181 is not performing an external memory access, then
it responds to the active

BR input in the following processor

cycle by:

· three-stating the data and address buses and the

PMS, DMS,

BMS, CMS, IOMS, RD, WR output drivers,

· asserting the bus grant (

BG) signal, and

· halting program execution.

When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory ac-
cesses.

The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor and start execution at address 0 when
the BDMA accesses have completed.

Internal Memory DMA Port (IDMA Port)

The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2181. The port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP's memory-
mapped control registers.

The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
ADSP-2181 is operating at full speed.

The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This in-
creases throughput as the address does not have to be sent for
each memory access.

IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-
bit address and 1-bit destination type can be driven onto the bus
by an external device. The address specifies an on-chip memory
location; the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.

Once the address is stored, data can either be read from or
written to the ADSP-2181's on-chip memory. Asserting the
select line (

IS) and the appropriate read or write line (IRD and

IWR respectively) signals the ADSP-2181 that a particular
transaction is required. In either case, there is a one-processor-
cycle delay for synchronization. The memory access consumes
one additional processor cycle.

Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.

Bootstrap Loading (Booting)

The ADSP-2181 has two mechanisms to allow automatic load-
ing of the on-chip program memory after reset. The method for
booting after reset is controlled by the MMAP and BMODE
pins as shown in Table VI.

REV. D

ADSP-2181

If Go Mode is enabled, the ADSP-2181 will not halt program
execution until it encounters an instruction that requires an
external memory access.

If the ADSP-2181 is performing an external memory access
when the external device asserts the

BR signal, then it will not

three-state the memory interfaces or assert the

BG signal until

the processor cycle after the access completes. The instruction
does not need to be completed when the bus is granted. If a
single instruction requires two external memory accesses, the
bus will be granted between the two accesses.

When the

BR signal is released, the processor releases the BG

signal, reenables the output drivers and continues program
execution from the point where it stopped.

The bus request feature operates at all times, including when
the processor is booting and when

RESET is active.

The

BGH pin is asserted when the ADSP-2181 is ready to

execute an instruction, but is stopped because the external bus
is already granted to another device. The other device can re-
lease the bus by deasserting bus request. Once the bus is re-
leased, the ADSP-2181 deasserts

BG and BGH and

executes

the external memory access.

Flag I/O Pins

The ADSP-2181 has eight general purpose programmable in-
put/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc-
tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2181's
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2181 has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.

INSTRUCTION SET DESCRIPTION

The ADSP-2181 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of the
processor's unique architecture, offers the following benefits:

· The algebraic syntax eliminates the need to remember cryptic

assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.

· Every instruction assembles into a single, 24-bit word that can

execute in a single instruction cycle.

· The syntax is a superset ADSP-2100 Family assembly lan-

guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
2181's interrupt vector and reset vector map.

· Sixteen condition codes are available. For conditional jump,

call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.

· Multifunction instructions allow parallel execution of an

arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2181 has on-chip emulation support and an ICE-
Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE

's in-circuit probe, a 14-pin plug.

The ICE-Port interface consists of the following ADSP-2181 pins:
EBR

EMS

ELIN

EBG

EINT

ELOUT

ERESET

ECLK

These ADSP-2181 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the ADSP-
2181 and the connector must be kept as short as possible, no
longer than three inches.

The following pins are also used by the EZ-ICE:
BR

GND

RESET

The EZ-ICE

uses the EE (emulator enable) signal to take con-

trol of the ADSP-2181 in the target system. This causes the
processor to use its

ERESET, EBR and EBG pins instead of the

RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.

The EZ-ICE

connects to the target system via a ribbon cable

and a 14-pin female plug. The ribbon cable is 10 inches in
length with one end fixed to the EZ-ICE. The female plug is
plugged onto the 14-pin connector (a pin strip header) on the
target board.

Target Board Connector for EZ-ICE

Probe

The EZ-ICE

connector (a standard pin strip header) is shown in

Figure 7. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE

probe onto the 14-pin

connector.

GND

KEY (NO PIN)

RESET

TOP VIEW

EBG

EBR

ELOUT

EINT

ELIN

ECLK

EMS

ERESET

Figure 7. Target Board Connector for EZ-ICE

ADSP-2181

REV. D

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion--you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 x 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie and Samtec.

Target Memory Interface

For your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines listed
below.

PM, DM, BM, IOM and CM

Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM) and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP's data sheet. The performance of the
EZ-ICE

may approach published worst case specification for

some memory access timing requirements and switching
characteristics.

Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.

Restriction: All memory strobe signals on the ADSP-2181
(

RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your

target system must have 10 k

pull-up resistors connected when

the EZ-ICE

is being used. The pull-up resistors are necessary

because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE

debugging sessions. These resistors may be removed at

your option when the EZ-ICE

is not being used.

Target System Interface Signals

When the EZ-ICE

board is installed, the performance on some

system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE

board:

· EZ-ICE

emulation introduces an 8 ns propagation delay be-

tween your target circuitry and the DSP on the

RESET

signal.

· EZ-ICE

emulation introduces an 8 ns propagation delay be-

tween your target circuitry and the DSP on the

BR signal.

· EZ-ICE

emulation ignores

RESET and BR when single-

stepping.

· EZ-ICE

emulation ignores

RESET and BR when in Emulator

Space (DSP halted).

· EZ-ICE

emulation ignores the state of target

BR in certain

modes. As a result, the target system may take control of the
DSP's external memory bus only if bus grant (

BG) is asserted

by the EZ-ICE

board's DSP.

Target Architecture File

The EZ-ICE

software lets you load your program in its linked

(executable) form. The EZ-ICE

PC program can not load sec-

tions of your executable located in boot pages (by the linker).
With the exception of boot page 0 (loaded into PM RAM), all
sections of your executable mapped into boot pages are not
loaded.

Write your target architecture file to indicate that only PM
RAM is available for program storage, when using the EZ-ICE
software's loading feature. Data can be loaded to PM RAM or
DM RAM.

ADSP-2181SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

Parameter

Min

Max

Min

Max

Unit

Supply Voltage

4.5

5.5

4.5

5.5

AMB

Ambient Operating Temperature

+70

+85

ELECTRICAL CHARACTERISTICS

K/B Grades

Parameter

Test Conditions

Min

Typ

Max

Unit

Hi-Level Input Voltage

1, 2

@ V

= max

2.0

Hi-Level CLKIN Voltage

@ V

= max

2.2

Lo-Level Input Voltage

1, 3

@ V

= min

0.8

Hi-Level Output Voltage

1, 4, 5

@ V

= min

= 0.5 mA

2.4

@ V

= min

= 100

0.3

Lo-Level Output Voltage

1, 4, 5

@ V

= min

= 2 mA

0.4

Hi-Level Input Current

@ V

= max

= V

max

Lo-Level Input Current

@ V

= max

= 0 V

OZH

Three-State Leakage Current

@ V

= max

= V

max

OZL

Three-State Leakage Current

@ V

= max

= 0 V

Supply Current (Idle)

@ V

= 5.0

AMB

= +25

= 34.7 ns

= 30 ns

= 25 ns

Supply Current (Dynamic)

@ V

= 5.0

AMB

= +25

= 34.7 ns

= 30 ns

= 25 ns

Input Pin Capacitance

3, 6, 12

@ V

= 2.5 V,

= 1.0 MHz,

AMB

= +25

Output Pin Capacitance

6, 7, 12, 13

@ V

= 2.5 V,

= 1.0 MHz,

AMB

= +25

NOTES

Bidirectional pins: D0D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1A13, PF0PF7.

Input only pins:

RESET, BR, DR0, DR1, PWD.

Input only pins: CLKIN,

RESET, BR, DR0, DR1, PWD.

Output pins:

BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.

Although specified for TTL outputs, all ADSP-2186 outputs are CMOS-compatible and will drive to V

and GND, assuming no dc loads.

Guaranteed but not tested.

Three-statable pins: A0A13, D0D23,

PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0PF7.

0 V on

BR, CLKIN Inactive.

Idle refers to ADSP-2181 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V

or GND.

measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2

and type 6, and 20% are idle instructions.

= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

Applies to TQFP and PQFP package types.

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

REV. D

ADSP-2181

REV. D

ESD SENSITIVITY

The ADSP-2181 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges.

The ADSP-2181 features proprietary ESD protection circuitry to dissipate high energy discharges
(Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-2181 has been classified as
a Class 1 device.

Proper ESD precautions are recommended to avoid performance degradation or loss of function-
ality. Unused devices must be stored in conductive foam or shunts, and the foam should be
discharged to the destination before devices are removed.

TIMING PARAMETERS

GENERAL NOTES

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.

TIMING NOTES

Switching Characteristics specify how the processor changes its
signals. You have no control over this timing--circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switch-
ing characteristics to ensure that any timing requirement of a
device connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.

MEMORY TIMING SPECIFICATIONS

The table below shows common memory device specifications
and the corresponding ADSP-2181 timing parameters, for your
convenience.

Memory

ADSP-2181 Timing

Device

Timing

Parameter

Specification

Parameter

Definition

Address Setup to

ASW

A0A13,

xMS Setup before

Write Start

WR Low

Address Setup to

A0A13,

xMS Setup before

Write End

WR Deasserted

Address Hold Time

WRA

A0A13,

xMS Hold after

WR Deasserted

Data Setup Time

Data Setup before

High

Data Hold Time

Data Hold after

WR High

OE to Data Valid

RDD

RD Low to Data Valid

Address Access Time t

A0A13,

xMS to Data Valid

xMS = PMS, DMS, BMS, CMS, IOMS.

FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS

is defined as 0.5t

CKI

. The ADSP-2181 uses an input clock

with a frequency equal to half the instruction rate: a 16.67 MHz
input clock (which is equivalent to 60 ns) yields a 30 ns proces-
sor cycle (equivalent to 33 MHz). t

values within the range of

0.5t

CKI

period should be substituted for all relevant timing pa-

rameters to obtain the specification value.

Example: t

CKH

= 0.5t

7 ns = 0.5 (25 ns) 7 ns = 8 ns

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Operating Temperature Range (Ambient) . . . . 40

C to +85

Storage Temperature Range . . . . . . . . . . . . . 65

C to +150

Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . +280

Lead Temperature (5 sec) PQFP . . . . . . . . . . . . . . . . . +280

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

WARNING!

ESD SENSITIVE DEVICE

ADSP-2181

REV. D

Parameter

Min

Max

Unit

Serial Ports

Timing Requirements:
t

SCK

SCLK Period

SCS

DR/TFS/RFS Setup before SCLK Low

SCH

DR/TFS/RFS Hold after SCLK Low

SCP

SCLK

Width

Switching Characteristics:
t

CLKOUT High to SCLK

OUT

0.25t

+ 10

SCDE

SCLK High to DT Enable

SCDV

SCLK High to DT Valid

TFS/RFS

OUT

Hold after SCLK High

TFS/RFS

OUT

Delay from SCLK High

SCDH

DT Hold after SCLK High

TDE

TFS (Alt) to DT Enable

TDV

TFS (Alt) to DT Valid

SCDD

SCLK High to DT Disable

RDV

RFS

(Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

SCLK

TFS

OUT

RFS

OUT

ALTERNATE

FRAME MODE

SCS

SCH

SCDE

SCDH

SCDD

TDE

RDV

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

TFS

RFS

OUT

TFS

OUT

TDV

SCDV

SCP

SCK

SCP

TFS

RFS

ALTERNATE

FRAME MODE

RDV

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

TDV

TDE

Figure 13. Serial Ports

ADSP-2181

REV. D

OUTPUT DRIVE CURRENTS

Figure 19 shows typical I-V characteristics for the output drivers
of the ADSP-2181. The curves represent the current drive
capability of the output drivers as a function of output voltage.

SOURCE VOLTAGE Volts

SOURCE CURRENT mA

120

80

100

20

40

60

5.5V, 40 C

5.0V, +25 C

4.5V, +85 C

5.0V, +25 C

5.5V, 40 C

Figure 19. Typical Drive Currents

POWER DISSIPATION

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

C = load capacitance, f = output switching frequency.

Example:

In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:

Assumptions:

External data memory is accessed every cycle with 50% of the
address pins switching.

External data memory writes occur every other cycle with
50% of the data pins switching.

Each address and data pin has a 10 pF total load at the pin.

The application operates at V

= 5.0 V and t

= 30 ns.

Total Power Dissipation = P

INT

+ (C

f )

INT

= internal power dissipation from Power vs. Frequency

graph (Figure 20).

TEMPERATURE 

1000

100

CURRENT (LOG SCALE) 

= 5.5V

= 5.0V

= 4.5V

NOTES:
1. REFLECTS ADSP-2181 OPERATION IN LOWEST POWER MODE.
(SEE "SYSTEM INTERFACE" CHAPTER OF THE

ADSP-2100 FAMILY

USER'S MANUAL, THIRD EDITION, FOR DETAILS.)
2. CURRENT REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

Figure 20. Power-Down Supply Current (Typical)

f ) is calculated for each output:

# of
Pins

Address,

DMS

10 pF

33.3 MHz

66.6 mW

Data Output,

WR 9

10 pF

16.67 MHz =

37.5 mW

10 pF

16.67 MHz =

4.2 mW

CLKOUT

10 pF

33.3 MHz

8.3 mW

116.6 mW

Total power dissipation for this example is P

INT

+ 116.6 mW.

1/t

 MHz

POWER (P

INT

) mW

220

420

370

320

270

570

470

520

2181 POWER, INTERNAL

1, 3, 4

= 5.5V

= 5.0V

= 4.5V

410mW

325mW

250mW

550mW

425mW

330mW

POWER (P

IDLE

) mW

1/t

 MHz

100

POWER, IDLE

1, 2, 3

= 5.5V

= 5.0V

= 4.5V

77mW

60mW

45mW

95mW

75mW

54mW

1/t

 MHz

POWER (P

IDLE

) mW

POWER, IDLE

n MODES

IDLE

IDLE (16)
IDLE (128)

60mW

35mW

34mW

39mW

37mW

75mW

VALID FOR ALL TEMPERATURE GRADES.

MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL

MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14),
30% ARE TYPE 2 AND TYPE 6 AND 20% ARE IDLE INSTRUCTIONS.

TYPICAL POWER DISSIPATION AT 5.0V V

AND 25 C EXCEPT WHERE SPECIFIED.

IDLE REFERS TO ADSP-2181 STATE OF OPERATION DURING EXECUTION OF IDLE

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V

OR GND.

Figure 21. Power vs. Frequency

REV. D

ADSP-2181

CAPACITIVE LOADING

Figures 22 and 23 show the capacitive loading characteristics of
the ADSP-2181.

 pF

RISE TIME (0.4V

2.4V

) ns

100

150

200

250

Figure 22. Range of Output Rise Time vs. Load Capaci-
tance, C

(at Maximum Ambient Operating Temperature)

 pF

VALID OUTPUT DELAY OR HOLD ns

100

150

250

200

Figure 23. Range of Output Valid Delay or Hold vs. Load
Capacitance, C

(at Maximum Ambient Operating

Temperature)

TEST CONDITIONS
Output Disable Time

Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (t

DIS

) is the difference of t

MEASURED

and t

DECAY

as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low volt-
age level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
t

DECAY

, is dependent on the capacitive load, C

, and the current

load, i

, on the output pin. It can be approximated by the fol-

lowing equation:

DECAY

0.5V

from which

DIS

MEASURED

DECAY

is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.

1.5V

INPUT

OUTPUT

1.5V

Figure 24. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t

ENA

) is the interval from when

a reference signal reaches a high or low voltage level to when
the output has reached a specified high or low trip point, as
shown in the Output Enable/Disable diagram. If multiple pins
(such as the data bus) are enabled, the measurement value is
that of the first pin to start driving.

2.0V

1.0V

ENA

REFERENCE

SIGNAL

OUTPUT

DECAY

(MEASURED)

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

DIS

MEASURED

(MEASURED)

(MEASURED) 0.5V

(MEASURED) +0.5V

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

(MEASURED)

Figure 25. Output Enable/Disable

OUTPUT

PIN

50pF

+1.5V

Figure 26. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)

ADSP-2181

REV. D

TQFP Pin Configurations

TQFP

Pin

TQFP

Pin

TQFP

Pin

TQFP

Pin

Number

Name

Number

Name

Number

Name

Number

Name

IAL

A12

ECLK

D19

PF3

A13

ELOUT

D20

PF2

IRQE

ELIN

D21

PF1

MMAP

EINT

100

D22

PF0

PWD

EBR

101

D23

IRQ2

102

GND

BMODE

EBG

103

IWR

IOMS

PWDACK

104

IRD

BMS

IACK

VDD

105

IAD15

DMS

BGH

106

IAD14

CMS

VDD

107

IAD13

GND

108

IAD12

VDD

IRQL0

109

IAD11

PMS

IRQL1

110

IAD10

FL0

GND

111

IAD9

FL1

112

IAD8

FL2

113

IAD7

DT0

114

IAD6

TFS0

115

VDD

RFS0

116

GND

DR0

D10

117

IAD5

SCLK0

D11

118

IAD4

XTAL

DT1/F0

D12

119

IAD3

CLKIN

TFS1/

IRQ1

D13

120

IAD2

GND

RFS1/

IRQ0

D14

121

IAD1

CLKOUT

GND

122

IAD0

GND

DR1/FI

VDD

123

PF7

VDD

SCLK1

GND

124

PF6

ERESET

D15

125

PF5

RESET

D16

126

PF4

A10

EMS

D17

127

GND

A11

D18

128

ADSP-2181

REV. D

PQFP Pin Configurations

PQFP

Pin

PQFP

Pin

PQFP

Pin

PQFP

Pin

Number

Name

Number

Name

Number

Name

Number

Name

PF0

PWD

EBR

D23

IRQ2

GND

BMODE

EBG

IWR

IOMS

PWDACK

100

IRD

BMS

IACK

VDD

101

IAD15

DMS

BGH

102

IAD14

CMS

VDD

103

IAD13

GND

104

IAD12

VDD

IRQL0

105

IAD11

PMS

IRQL1

106

IAD10

FL0

GND

107

IAD9

FL1

108

IAD8

FL2

109

IAD7

DT0

110

IAD6

TFS0

111

VDD

RFS0

112

GND

DR0

D10

113

IAD5

SCLK0

D11

114

IAD4

XTAL

DT1/FO

D12

115

IAD3

CLKIN

TFS1/

IRQ1

D13

116

IAD2

GND

RFS1/

IRQ0

D14

117

IAD1

CLKOUT

GND

118

IAD0

GND

DR1/FI

VDD

119

PF7

VDD

SCLK1

GND

120

PF6

ERESET

D15

121

PF5

RESET

D16

122

PF4

A10

EMS

D17

123

GND

A11

D18

124

A12

ECLK

D19

125

IAL

A13

ELOUT

D20

126

PF3

IRQE

ELIN

D21

127

PF2

MMAP

EINT

D22

128

PF1

REV. D

ADSP-2181

ORDERING GUIDE

Ambient

Instruction

Temperature

Rate

Package

Part Number

Range

(MHz)

Description

Options*

ADSP-2181KST-115

C to +70

28.8

128-Lead TQFP

ST-128

ADSP-2181BST-115

C to +85

28.8

128-Lead TQFP

ST-128

ADSP-2181KS-115

C to +70

28.8

128-Lead PQFP

S-128

ADSP-2181BS-115

C to +85

28.8

128-Lead PQFP

S-128

ADSP-2181KST-133

C to +70

33.3

128-Lead TQFP

ST-128

ADSP-2181BST-133

C to +85

33.3

128-Lead TQFP

ST-128

ADSP-2181KS-133

C to +70

33.3

128-Lead PQFP

S-128

ADSP-2181BS-133

C to +85

33.3

128-Lead PQFP

S-128

ADSP-2181KST-160

C to +70

128-Lead TQFP

ST-128

ADSP-2181KS-160

C to +70

128-Lead PQFP

S-128

*S = Plastic Quad Flatpack (PQFP), ST = Plastic Thin Quad Flatpack (TQFP).

OUTLINE DIMENSIONS

Dimensions shown in mm and (inches).

128-Lead Metric Plastic Quad Flatpack (PQFP)

(S-128)

102

128

103

TOP VIEW

(PINS DOWN)

0.45 (0.018)

0.30 (0.012)

0.87 (0.034)

0.73 (0.029)

31.45 (1.238)

30.95 (1.219)
28.10 (1.106)

27.90 (1.098)
24.87 (0.979)

24.73 (0.974)

31.45 (1.238)

30.95 (1.219)

28.10 (1.106)

27.90 (1.098)

24.87 (0.979)

24.73 (0.974)

SEATING

PLANE

4.07

(0.160)

MAX

1.03 (0.041)

0.65 (0.031)

0.10 (0.004)

MAX

0.25 (0.010)

MIN

3.67 (0.144)

3.17 (0.125)

NOTE: THE ACTUAL POSITION OF EACH LEAD IS

WITHIN .20 (.008) FROM ITS IDEAL POSITION
WHEN MEASURED IN THE LATERAL DIRECTION.
UNLESS OTHERWISE NOTED.

128-Lead Metric Thin Plastic Quad Flatpack (TQFP)

(ST-128)

TOP VIEW

(PINS DOWN)

0.27 (0.011)

0.17 (0.007)

16.25 (0.640)

15.75 (0.620)

18.50 (0.728) TYP

14.10 (0.555)

13.90 (0.547)

22.25 (0.876)

21.75 (0.856)

102

128

12.50 (0.492) TYP

0.58 (0.023)

0.42 (0.017)

103

20.10 (0.792)

19.90 (0.783)

SEATING

PLANE

1.60 (0.063)

TYP

0.75 (0.030)

0.45 (0.018)

0.10

(0.004)

MAX

1.50 (0.059)

1.30 (0.051)

0.15 (0.006)

0.05 (0.002)

NOTE: THE ACTUAL POSITION OF EACH LEAD IS

WITHIN .08 (.0032) FROM ITS IDEAL POSITION
WHEN MEASURED IN THE LATERAL DIRECTION.
UNLESS OTHERWISE NOTED.

C2041c33/98

PRINTED IN U.S.A.

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